Example embodiments relate to memory devices, and more particularly, to a memory device including a parallel bit test (PBT) circuit, and a memory system including the memory device.
With the development of memory systems including semiconductor memory devices, the number of semiconductor memory devices included in a single memory module or a memory system has gradually increased. Accordingly, a probability of occurrence of defects in semiconductor memory devices has also increased, and a test of detecting and sorting out these defects has become important.
In a general test for semiconductor memory devices, an external test apparatus writes data to memory cells of a semiconductor memory device that is tested, reads data from the memory cells, and compares read-out data with the written data to thereby determine whether the semiconductor memory device is good or defective.
As the storage capacity of semiconductor memory devices increases, a testing time period may increase. Thus, to improve the productivity of a process of manufacturing semiconductor memory devices, a demand for reducing the testing time increases. In response to this demand, a PBT circuit is typically used at an inspection stage of semiconductor memory devices.
In general, since volatile memory responds and operates at a high speed, the volatile memory is widely used as the main memory of a system. Generally, the volatile memory may write or read data under the control of a host.
DRAMs including a circuit that internally performs some calculation operations of a host have been recently developed. Since the workload on the host decreases, the entire performance of memory systems including such DRAMs may improve. However, a special interface for the internal operations may be required, leading to a cost increase for an apparatus for performing the internal operations.